The present invention relates to a semiconductor device, particularly to a structure of a Schottky. barrier.diode clamp transistor (below, SBD transistor). The SBD transistor according to the present invention is very effective for increasing the margin of an output voltage at a low level side, and improving a switching speed, when used as an output transistor of a logic circuit of a digital circuit, for example, TTL (Transistor Transistor Logic) or ECL (Emitter Coupled Logic).
As an example of a conventional logic circuit, a TTL circuit is shown in FIG. 1. As it is well known, the operation of the circuit shown in FIG. 1 is explained only briefly, as follows. That is, when both input voltages V.sub.IN1 and V.sub.IN2 become high (H) level, a base current of an input multiemitter transistor Tr.sub.1 flows to a base of a transistor Tr.sub.2 and the transistor Tr.sub.2 is turned ON, then an output transistor Tr.sub.4 is turned ON and an output voltage V.sub.OUT becomes low (L) level. Conversely, when any input voltage becomes L level, base charges of the transistor Tr.sub.2 are pulled out through a transistor gate and the transistor Tr.sub.2 is turned OFF. At that time, base charges of the output transistor Tr.sub.4 are pulled out to a ground (GND) side through a relatively low base resistor R.sub.B. At the same time, the transistor Tr.sub.3 connected to a collector of the transistor Tr.sub.2, which has been turned OFF before the final stage is turned OFF, is driven. The transistor Tr.sub.3 of the buffer stage operates to forcibly raise the collector potential of the output transistor Tr.sub.4 so that the switching speed of the transistor Tr.sub.4 can be raised. When a capacitive load exists at the output terminal, the capacitive load is quickly charged by the transistor Tr.sub.3 so that the output voltage V.sub.OUT is pulled up and becomes H level.
As explained above, the output Tr.sub.4 functions as an inverter transistor. In general, the TTL circuit employs a saturation type circuit which becomes saturated when the inverter transistor is turned ON. That is, the saturation area of the transistor is basically used in the TTL circuit, particularly, the output transistor passes a relatively large base current in order to raise the driving ability for the load connected to the next stage. For this reason, a driving factor representing a relationship between the base current and the collector current becomes, in general, 2 to 3. That is, the base current is multiplied by 2 to 3 times the collector current necessary for the switching operation flow in the base. This large base current has the result that when the output transistor is turned ON, that is, the output is L level, the saturated state becomes deep and the carrier accumulation at the base area is increased. As a countermeasure, although the discharge of base charges can be quickened by a gold diffusion method, there is a problem in that the switching time is delayed despite this method.
To solve this problem, there is a method using the SBD transistor, and the Schottky.barrier.diode (SBD), in which the forward direction voltage drop is rare, is provided between the base and the collector as shown in FIG. 2. The equivalent circuit of the output stage SBD transistor TR.sub.4 is shown in FIG. 3 and the cross-sectional view thereof is shown in FIG. 4. In FIG. 3, the terminals B, C, and E correspond to the base, the collector, and the emitter terminals of the output transistor TR.sub.4. SBD represents a Schottky.barrier.diode and constitutes a clamping circuit (in this case, only the SBD is shown and the clamping circuit becomes the "clamping element"). By this method, the Schottky. barrier.diode SBD is formed in the diffusion layer by utilizing the window of the same electrode as the base B, as shown in FIG. 4. Accordingly, the collector potential V.sub.0 is clamped by the formula V.sub.0 =V.sub.BE -V.sub.F, since there is no resistor in the clamping circuit; where V.sub.BE represents a base-emitter voltage of the equivalent circuit of the transistor shown in FIG. 3, and V.sub.F represents a voltage drop of the SBD. For example, if V.sub.BE =0.8 V and V.sub.F =0.4 V, V.sub.O becomes 0.4 V. As shown by a chain dotted straight line II in FIG. 5, the margin can be obtained to a V.sub.OLMAX =0.5 V since the V.sub.O is raised from 0.4 V, and thus the problem of saturation is solved and the delay of the switching speed is also solved. The straight line I shown by a dotted line in FIG. 5 represents the I.sub.O -V.sub.O characteristic in the case that the clamping circuit by the SBD does not exist, as shown in FIG. 1.
As shown in FIG. 5, however, although the potential of the leading edge of the L level can be pulled down in this method, the collector resistance R.sub.O (R.sub.O =a+b+c) is unconditionally decided based on the structure as shown by parasitic resistances a, b and c in FIG. 4. Therefore, the low level output voltage of the collector becomes the I.sub.O -V.sub.O characteristic of the straight line II shifting toward the high potential direction for the V.sub.F of the Schottky.barrier.diode SBD.
Meanwhile, as another conventional example (not shown) of the SBD transistor, the structure wherein the Schottky.multidot.barrier.multidot.diode SBD is provided to a separate window from the window of the base electrode of the base side B, is disclosed (Japanese Examined Patent Publication No. 47-21743, Priority: U.S. patent application Ser. No. No. 683,238). In this case, as shown in FIG. 4, the parasitic resistance of the collector side up to the point P.sub.1 or P.sub.2 is denoted by the sum b+c of the burying resistance b and the collector resistance c, and the collector parasitic resistance of the emitter side is denoted by reference character a. When the window of the SBD and the base B are located at the same place or are located in the vicinity of the base B, the parasitic resistance is given by the relationship b+c&gt;a. When the windows of the base B and the SBD are separated, an effect occurs whereby the resistance is inserted in series to the SBD under the parasitic resistance of the SBD side. Accordingly, as shown by the straight lines II.sub.X, II.sub.Y, and II.sub.Z of the chain dotted line in FIG. 5, it is possible to obtain the margin of the low level output voltage V.sub.0L. However, since the parasitic resistance b+c of the collector side becomes larger than the parasitic resistance a of the emitter side, as explained above, when the collector current I.sub.0 is intended to be set to a larger value, it is difficult to obtain such a large collector current since the V.sub.0L has reached the V.sub.OLMAX, as shown by the straight lines II.sub.X, II.sub.Y, and II.sub.Z.
As explained above, in the structure of the output transistor using a conventional SBD transistor, although the switching speed can be improved, there is a problem in that the margin of the V.sub.OL is reduced by dispersions of the forward direction voltage of the SBD and the base-emitter of the transistor. This means that an allowable extent of manufacturing dispersions becomes narrow, from the viewpoint of the manufacturer and as a result, the yield rate is lowered, the cost is increased, and moreover, the flexibilities of the circuit design of the device and of the layout on the printed circuit board are reduced, since the operation margin is reduced.